Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-End Microprocessors

Distributing high quality clock signals is one of the most challenging tasks in high-performance microprocessors. Clocking circuitry accounts for an overwhelming amount of total power consumption in multi-GHz processors. Unfortunately, deteriorating clock skew and jitter make it very difficult to reduce power dissipation. We propose a new global clocking scheme, injection-locked clocking (ILC), to combat clock skew and jitter. This new scheme uses injection-locked oscillators as the clock receivers. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. Unlike other proposed clocking schemes, ILC is fully compatible with conventional clock distribution. In this paper, a quantitative study based on circuitand microarchitectural-level simulations is conducted to verify the performance and power consumption improvements using ILC compared to conventional clocking. Alpha21264 is used as the baseline processor, and is scaled to 0.13μm technology and 3GHz. Two ILC configurations are constructed: one of them simply replaces the top-level global clock X/Htree in Alpha21264; another one is optimized for ILC operation. Both circuit and architectural simulations show 20ps and 23ps reduction in jitter, 10.1% and 17% power savings, respectively, using the two ILC configurations in comparison to the conventional clocking.